1. Field of the Invention
The present invention generally relates to memory systems and more specifically to a compression status bit cache with deterministic isochronous latency.
2. Description of the Related Art
Performance requirements are constantly increasing in data processing systems, which conventionally comprise one or more processor chips and attached memory devices. Each processor chip includes on-chip data processing resources and memory interface circuitry configured to enable the processing resources to access off-chip, attached memory devices. The processing resources typically include at least one isochronous subsystem, such as a video scan out subsystem configured to drive a display device. An isochronous subsystem generally requires deterministic access to the attached memory devices in order to reliably perform real-time tasks.
To improve overall performance, effective memory bandwidth to the attached memory devices may be increased by storing certain data in a compressed format, which reduces the number of bits needed to represent a block of original data. The amount of memory allocated to store a block of original data in a compressed format may not be not reduced compared to an uncompressed format, but the number of bits needed to store and retrieve the compressed block of data is reduced and therefore memory bandwidth is reduced. A plurality of both loss-less and lossy compressed formats may be used, depending on specific application requirements and whether a specific block of original data is compressible under available compression algorithms.
Each compression format advantageously reduces the number of bits needed to represent a block of original data stored as a compressed block within attached memory. Interpreting bits within the compressed block depends on which compression format, if any, is used to represent the block of original data. A selected compression format associated with each block is indicated by compression status bits for each block of compressible memory. To generate a memory access request that is sized to match a corresponding compressed format, the compressed format needs to be known prior to generating the memory access request. Therefore, a memory request generator circuit configured to generate the memory access request needs to refer to associated compression status bits prior to posting the memory access request to the attached memory.
To maximize performance, the compression status bits should be available to the memory request generator circuit from an on-chip source. A compression status bit cache may be used as an on-chip source of compression status bits for the memory request generator circuit. In normal operation, the compression status bit cache provides compression status bits that may be used to determine a memory access request size. In the event of a miss within the compression status bit cache, a cache line of data corresponding to the cache miss must be loaded by the compression status bit cache. However, to load a new cache line, a clean cache line must be available to be overwritten with the new cache line. If no clean cache line is available, the compression status bit cache must first identify and flush a dirty cache line in a process with no bounded completion time. Without a bounded completion time for compression status bit cache requests, an isochronous subsystem cannot be guaranteed to have deterministic memory access. One solution to this problem is to preclude isochronous subsystems from accessing compressed memory. However, such a restriction unreasonably limits applications from using compressed memory and increases overall bandwidth to attached memory devices.
Accordingly, what is needed in the art is a technique that enables isochronous subsystems to access compressed data within attached memory using a deterministic access regime.